The present invention relates to analog-to-digital converters, and more particularly to an analog-to-digital converter (ADC) using a sigma delta converter that fits into a class of converters known as sub-ranging ADCs.
A type of ADC known as a sub-ranging ADC has two converters and a digital-to-analog converter (DAC) to improve on the characteristics of a single monolithic converter. A typical architecture is shown in FIG. 1 where an analog signal is input to a sample and hold circuit. The output from the sample and hold circuit is input to a first monolithic ADC and to a difference amplifier. The output from the first ADC is input to a digital correction circuit and to a DAC. The output from the DAC is input to the difference amplifier, with the difference output being input to a second monolithic ADC. The output from the second ADC also is input to the digital correction circuit. The digital correction circuit typically has a random access memory (RAM) that is addressed by the output from the first ADC to provide an output that is added to the output from the second ADC to produce a converted digital signal corresponding to the input analog signal.
The performance of this architecture is primarily limited by two devices the sample and hold circuit and the DAC. A major part of the performance depends on the characterization of the DAC. DC quantization levels are easily corrected, but AC non-linearities are very difficult to correct, if done at all.
What is desired is a more accurate sub-ranging ADC that eliminates the requirement for correcting AC non-linearities.
Accordingly the present invention provides a sub-ranging analog-to-digital converter (ADC) using a sigma delta converter which eliminates both the sample and hold and digital-to-analog converter circuits of prior sub-ranging ADCs. An input analog signal is applied to a sigma delta modulator that provides a one-it output. The one-bit output is input to a first analog filter and a digital correction circuit. The output from the first analog filter and the input analog signal, suitably delayed and optionally filtered, are input to a difference amplifier that provides the input to an ADC. The output of the ADC also is input to the digital correction circuit. The digital correction circuit includes a digital decimation filter for the one-bit sigma delta modulator output to produce a multi-bit digital output that is added to the output from the ADC. The resulting summed digital signal may be additionally digitally filtered to produce a converted digital signal that corresponds to the input analog signal.
The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.